A. Field of Invention
This invention relates to the field of semiconductor design and fabrication. Specifically, this invention relates to the achievement of zero skew while routing a clock net.
B. Description of the Related Art
"Routing" in semiconductor fabrication involves determining wiring paths between elements on the surface of an integrated circuit. As is described more fully below, clocks require special attention during the routing process. It is desirable to have a clock signal reach all the functional elements to which the clock is connected at the same time. This allows a higher clock frequency thereby increasing the performance of the integrated circuit. As is described more fully herein, the present invention involves clock routing and related techniques for increasing chip performance.
1. Integrated Circuit Basics
An integrated circuit chip (hereafter referred to as an "IC" or a "chip") comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected, thus connecting the logic circuits having the pins. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins, that must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins.
The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins or thousands or tens of thousands to be connected. A netlist is a list of nets including names of connected pins or a list of cells including names of nets that connect to pins of cells. Clock nets typically have around 100,000 flipflops.
2. Chip Fabrication
As mentioned above, the present invention involves the clock routing. Routing is one of the steps necessary for the fabrication of an IC. These additional steps are very well known by those skilled in the art of semiconductor fabrication and are briefly described below.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks arc used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Currently, the minimum geometric feature size of a component is on the order of 0.2 microns. However, it is expected that the feature size can be reduced to 0.1 micron within the next few years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An exemplary integrated circuit chip is illustrated in FIG. 1 and generally designated by the reference numeral 26. The circuit 26 includes a semiconductor substrate 26A on which are formed a number of functional circuit blocks that can have different sizes and shapes. Some arc relatively large, such as a central processing unit (CPU) 27, a read-only memory (ROM) 28, a clock/timing unit 29, one or more random access memories (RAM) 30 and an input/output (I/O) interface unit 31. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries.
The integrated circuit 26 further comprises a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells 32. Each cell 32 represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
The cells 32 and the other elements of the circuit 26 described above are interconnected or routed in accordance with the logical design of the circuit to provide the desired functionality. Although not visible in the drawing, the various elements of the circuit 26 are interconnected by electrically conductive lines or traces that are routed, for example, through vertical channels 33 and horizontal channels 34 that run between the cells 32.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
Partitioning. A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore it is normally partitioned by grouping the components into blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
Floor planning and placement. This step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
Routing. The objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels and switch boxes. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel and switch boxes.
Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes channel routing and switch box routing.
Compaction. Compaction is the task of compressing the layout in all directions such that the total area is reduced. By making the chips smaller, wire lengths are reduced which in turn reduces the signal delay between components of the circuit. At the same time a smaller area enables more chips to be produced on a wafer which in turn reduces the cost of manufacturing. Compaction must ensure that no rules regarding the design and fabrication process are violated.
Wafer Construction. Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer (film) of light-sensitive material, such as photoresist. Using a patterned mask or reticle, the wafer is exposed to projected light, typically actinic light, which manifests a photochemical effect on the photoresist, which is subsequently chemically etched, leaving a pattern of photoresist "lines" on the wafer corresponding to the pattern on the mask.
A "wafer" is a thin piece of semiconductor material from which semiconductor chips are made. The four basic operations utilized to fabricate wafers include (1) layering, (2) patterning, (3) doping and (4) heat treatments.
The layering operation adds thin layers of material, including insulators, semiconductors, and conductors, to a wafer surface. During the layering operation, layers are either grown or deposited. Oxidation involves growing a silicon dioxide (an insulator) layer on a silicon wafer. Deposition techniques include, for example, chemical vapor deposition, evaporation, and sputtering. Semiconductors are generally deposited by chemical vapor deposition, while conductors are generally deposited with evaporation or sputtering.
Patterning involves the removal of selected portions of surface layers. After material is removed, the wafer surface has a pattern. The material removed may form a hole or an island. The process of patterning is also known to those skilled in the relevant art as microlithography, photolithography, photomasking and masking. The patterning operation serves to create parts of the semiconductor device on the wafer surface in the dimensions required by the circuit design and to locate the parts in their proper location on the wafer surface.
Doping involves implanting dopants in the surface of the wafer through openings in the layers to create the n-type and p-type pockets needed to form the N-P junctions for operation of discrete elements such as transistors and diodes. Doping is generally achieved with thermal diffusion (wafer is heated and exposed to the desired dopant) and ion implantation (dopant atoms are ionized, accelerated to high velocities and implanted into the wafer surface).
3. Zero Skew Routing of Clock Nets
Clock nets in very large scale integration systems need special attention with respect to routing. The performance of an IC is proportional to clock frequency. Clock nets need to be routed with precision since the actual length of the path of a net from its entry point to its terminals determines the maximum clock frequency on which a chip may operate. Accordingly, it is preferable that the clock signal arrive simultaneously at all functional units.
In reality, clock signals do not arrive at all functional units simultaneously. The maximum difference in the arrival time of a clock at two different components is called "skew." Thus, the goal in routing clock nets is to achieve as close to "zero skew" as is possible.
Accordingly, the chip designer is faced with the following problem: Given a clock driver and a number of flip-flops distributed arbitrarily on a chip, find a route from the clock driver to each of the flip-flops such that when a clock signal is sent from the driver, the delay to each of the flip-flops (because of the parasitic capacitances of the wires) is about the same, or alternatively, skew which is defined to be the difference between the largest delay and the smallest delay is close to zero.
The classical zero skew routing of Tsay builds a zero skew bottom-up tree, by choosing two pins under which the skew is zero, merging them by routing, and then finding a balance point (which will be the new tapping point) from which delays to all the bottom level flip-flops below this balance point are the same. A copy of Tsay's article "Exact Zero Skew," published in 1991 is attached hereto as Appendix 1 and incorporated herein by this reference as though set forth in full. In this case, such a balance point does not exist (because the delay to the flip-flops below one of the pins is much larger than that of the other), it adds enough wire in the route so that the delays are now equal if the tapping point is placed at the pin with the larger delay to all its bottom level flip-flops. Tsay uses the Elmore Delay model because of its mathematical elegance and ease of use. This delay model approximates the real delay well for clock trees. A copy of Elmore's article "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers," is attached as Appendix 2 and incorporated herein by this reference as though set forth in full.
Although Tsay's approach can be theoretically carried all the way up to the clock driver, certain practical considerations obviate its implementation. Electrical considerations imply that the driver will be driving much current, and hence the wire coming out of the driver needs to be very thick to handle such heavy currents. So if one is trying to do a zero skew route all the way to the top, one runs out of routing resources quickly because routing extremely thick wires at the top level becomes problematic due to the interference of wires already routed.
For this reason, some space (a preroute) is normally reserved which is used for routing at the top level to the driver. For symmetry, this preroute is generally an H trunk, whose middle wire and legs are much thicker than the wires that are used for lower level zero skew routing, and the driver then connects to the center of the middle wire.
This is shown in FIG. 3. Shown in FIG. 3 is an H trunk 100 comprising a left segment 105, a middle segment 103 and a right segment 104. The driver 101 is connected to the center 102 of the middle segment. The H trunk is connected to various flip-flops (1, 2, 3 and 4).
In the presence of an H trunk, the zero skew routing then proceeds in the following manner. First, the die is divided into four quadrants, top-left, top-right, bottom-left, and bottom-right. The pins in each quadrant are independently routed using Tsay's algorithm until there is one tapping point in each of the four quadrants. These four tapping points are then connected to the four apexes of the H. The pairing of tapping points to apexes can be done so as to minimize total wirelength used. But now a natural question presents itself. Although the delay from each tapping point to its respective bottom level flip-flops is the same, the inter-quadrant delays are not. So how does one ensure that one gets zero skew? A natural solution is to add enough wire on the smaller delay sides so that the delays are equalized. However, because of the details of the Elmore Delay, the computation of the exact amount of wire to be added in different quadrants is a non-trivial problem. The purpose of the present invention is to allow computation of the wirelengths that need to be added to achieve zero skew. In particular, this involves an efficient solution of two simultaneous quadratic equations in two variables. After computation of the wirelengths that need to be added to achieve zero skew, the routing process is completed with the additional wirelengths added and the steps described above with respect to semiconductor fabrication are executed and the IC is manufactured.